MRISC32 is a 32-bit RISC/Vector instruction set architecture (ISA).

The focus is to create a clean, modern ISA that is equally attractive to software, hardware and compiler developers. Another key goal is to enable high performance implementations, with good scalar and vector integer, floating point and fixed point support.

The ISA is primarily inspired by the Cray-1 and MIPS architectures, and is further influenced by the RISC-V architecture (in particular "Design of the RISC-V Instruction Set Architecture" by Andrew Waterman).




MRISC32-A1 9-stage pipeline

The first implementation of the MRISC32 ISA is MRISC32-A1, which is a soft processor implemented in portable VHDL, suitable for running on an FPGA. It is a 9-stage pipelined, single issue, in order architecture (i.e. it can execute at most one operation per clock cycle), and it implements the entire MRISC32 ISA.

The CPU easily fits in a low- to mid-range FPGA, such as the MAX® 10, in which it consumes about 12K logic elements and runs at 70-100 MHz at the time of writing. It can also be configured to use much less resources (down to 30% of the full design) by disabling certain features, such as floating point support.


MC1 diagram

The MC1 (short for MRISC32 Computer 1), is a small open source computer for FPGA:s, hosting an MRISC32-A1 CPU core. One of its main features is its flexible video subsystem that makes it suitable for graphical applications.


The MRSIC32 ISA and the MRISC32-A1 implementation are still in development. Several aspects such as exception handling and memory management are still undefined.