MRISC32, short for "Mostly harmless Reduced Instruction Set Computer, 32-bit edition", is a 32-bit RISC/Vector instruction set architecture (ISA).

The focus is to create a clean, modern ISA that is equally attractive to software, hardware and compiler developers. Another key goal is to enable high performance implementations, with good scalar and vector integer, floating point and fixed point support.

The ISA is primarily inspired by the Cray-1 and MIPS architectures, and is further influenced by the excellent RISC-V architecture (in particular "Design of the RISC-V Instruction Set Architecture" by Andrew Waterman).

Features

Implementations

MRISC32-A1

MRISC32-A1 9-stage pipeline

The first implementation of the MRISC32 ISA is MRISC32-A1, which is a soft processor implemented in portable VHDL, suitable for running on an FPGA. It is a 9-stage pipelined, single issue, in order architecture (i.e. it can execute at most one operation per clock cycle), and it implements the entire MRISC32 ISA.

The CPU easily fits in a low- to mid-range FPGA, such as the Cyclone® V, in which it consumes about 5000 ALM:s and runs at around 80 MHz at the time of writing. It can also be configured to use much less resources (down to 30% of the full design) by disabling certain features, such as floating point support.

Planned

Future designs in the "A" series (A2+) will use the same simple in-order principles as the A1, but increase vector parallelism in one or more of the following ways:

Superscalar Tomasulo-based implementations of the ISA are planned for the "B" series.

Status

The MRSIC32 ISA and the MRISC32-A1 implementation are still in development. Several aspects such as exception handling and memory management are still undefined.